Modern semiconductor memory devices, such as memory device 10 shown in FIG. 1, often have arrays of memory cells divided into two or more blocks. For example, conventional memory device 10 is shown with arrays 12a, 12b, 12c and 12d arranged as blocks. The memory device 10 is laid out on a integrated circuit substrate and supporting circuitry such as word line selection circuitry 14, bit line selection circuitry 16 and associated peripheral circuitry 18 is positioned around the memory arrays 12a and 12b. In determining the physical layout of memory device 10 on a substrate, the number of memory array blocks must be considered. In order to increase speed, memory device 10 should be divided into a large number of array blocks so that the bit line and word line components are minimized (i.e., with a large number of array blocks these lines will be shorter, allowing for faster read and write operations). However, from the point of view of reducing die size, a small number of array blocks is preferred.
In addition to the number of array blocks, several other conditions ultimately must be harmonized to determine the final physical layout of any semiconductor memory device. For example, the particular aspect ratio of the semiconductor substrate on which the memory device will be fabricated must be determined. The desire to make the speed of the memory device as fast as possible tends to push the chip aspect ratio, i.e., the ratio of a long edge of the die to a short edge of the die, to be square (i.e., approximately 1:1). This is because having a square aspect ratio will tend to minimize (overall) the length of interconnect structures (such as word lines and bit lines) within the memory device. However, packaging constraints, such as may be imposed by external standards which define the pin spacing and chip cavity size, must also be considered. Often these other constraints will necessitate aspect ratios of approximately 2:1 or 3:1.
In addition to aspect ratio, the pad locations for connection to external pins must be accommodated. Generally, for ease of packaging, bond pads should be placed on all four die edges with equal radial distance between the pads. However, in order to minimize die size, it is sometimes desirable to place the pads on only two opposite sides of the die.
Another important design consideration is keeping the array active current to a minimum. This is usually done by selecting a small number of cells within a block during read or write operations and by selecting only one block at time.
The position of the row and column decoders (shown as word line and bit line selectors 14 and 16 in FIG. 1) is another consideration and often involves a speed/die size trade off. Speed is generally improved when row and column decoders are placed at the center of die, however, die size is generally reduced when row and column decoders are placed at the edge of the die.
Thus, what is needed is a semiconductor memory device architecture that harmonizes each of the above design considerations.